Serge Leef
General Manager
System-Level Engineering Division
Mentor Graphics

System-Level Implications of Nanometer Design: Commercial EDA Opportunity or Nano-Niche?
It is widely believed nanometer designs will become increasingly common. In addition to challenging physical design and verification tools, this trend will force engineers to face and address serious problems in system-level design. 

While the emerging 100+ million gate chips will be manufacturable, they pose huge challenges in architectural specification, refinement and optimization; IP selection, evaluation and integration; system-wide analysis of performance and power; full system validation and implementation. How many design teams will really push the complexity to its limits?

Examine system-level design challenges as they apply to IP-dominant, bus-centric systems. Then, explore the economic forces that will either make these problems common to most designs or relegate them to a small number of teams focusing on ultra-high volume applications.

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