Monday, Oct. 15

8-8:15 a.m.

Registration/Breakfast

8:15-8:30 a.m.

Welcome, Vincent Mooney, General Chair, and Paul Hasler, Program Co-Chair

8:30-9:30 a.m.

Keynote: Serge Leef
Chair: Vincent Mooney

9:30-10 a.m.

Break

10-11:30 a.m.

Session 1
Analog Circuit Design
Chair: Kenneth W. Hsu, Rochester Institute of Technology

Session 2
CAD Tools
Chair: Wayne Wolf  (Georgia Tech)

1.1 “Power Invariant Secure IC Design Methodology Using Reduced Complementary Dynamic and Differential Logic,” Vijay Sundaresan, Srividhya Rammohan, and Ranga Vemuri (Univ. of Cincinnati)

B2.1 “ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching,” Marco Paolieri*, Ivano Bonesana*, and Marco Domenico Santambrogio**  (*Univ. of Lugano, Switzerland; **Politechnico di Milano, Italy)

1.2 “Neuromorphic Building Blocks for Adaptable Cortical Feature Maps,” C.M. Markan and Priti Gupta (Dayalbagh Educational Institute)

B2.2 “Use of Gray Decoding for Implementation of Symmetric Functions,” Osnat Keren*, Ilya Levin**, and Radomir Stankovic*** (*Bar Ilan Univ., Israel; **Tel Aviv Univ.; *** Univ. of Nis, Yugoslavia)

1.3 “An Analog Programmable Multi-Dimensional Radial Basis Function Based Classifier,” Sheng-Yu Peng, Paul Hasler, and David Anderson (Georgia Institute of Technology)

2.3 “Parametric Structure-Preserving Model Order Reduction,” Jorge Fernandez Villena*, Wil Schilders**, and L. Miguel Silveira* (*Technical Univ. of Eindhoven; ** NXP Semiconductors Research)

11:30-1 p.m.

Lunch

1-2:30 p.m.

Session 3
Modeling and Simulation
Chair: David Atienza Alonso (Universidad Complutense de Madrid)

Session 4
Reconfigurable System
Chair: Flavio Wagner (UFRGS)

3.1 “Hierarchical Statistical Analysis of Performance Variation for Continuous-Time Delta-Sigma Modulators,” Hua Tang (Univ. Minnesota)

B4.1 “A Software-Supported Methodology for Designing High-Performance 3D FPGA Architectures,” Kostas Siozios*, Kostas Sotiriadis* and Dimitrios Soudris* , Vassilis F. Pavlidis**(*Democritus Univ. of Thrace; **Univ. of Rochester)

3.2 “First Order Quasi-Static SOI MOSFET Channel Capacitance Model.” Sameer Sharma and Louis Johnson (Oklahoma State Univ.)

B4.2 “Estimating Design Time for System Circuits,” Cyrus Bazeghi*, Javi Martinez*, Brian Greskamp**, Josep Torrellas**, and Jose Renau* (*Univ. of California, Santa Cruz; ** Univ. of Illinois at Urbana-Champaign)

3.3 “Regression based Circuit Matrix Models for Accurate Performance Estimation of Analog Circuits,”  Almitra Pradhan and Ranga Vemuri (Univ. of Cincinnati)

B4.3 “Transparent Acceleration of Data Dependent Instructions for General Purpose Processors,” Antonio Carlos Schneider Beck and Luigi Carro (UFRGS)

2:30-3:30 p.m.

Break/Poster

3:30-5 p.m.

Session 5
Communication
Chair: Subhasish Mitra (Stanford)

Session 6
High-Level Synthesis
Chair: Amara Amara (Institut Superieur D’Electronique de Paris)

5.1 “VLSI Models of Network-on-Chip Interconnect,” Dimitrios Serpanos (Univ. of Patras) and Wayne Wolf (Georgia Institute of Technology)

6.1 Obtaining Delay Distribution of Dynamic Logic Circuits by Error Propagation at the Electrical Level,” Lucas Brusamarello, Roberto da Silva, Gilson Wirth, and Ricardo Reis (UFRGS)

5.2 “Statistical Analysis of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90 nm CMOS Technologies,” Gustavo Neuberger, Fernanda Kastensmidt, Ricardo Reis, Gilson Wirth, Ralf Brederlow, and Christian Pacha (UFRGS)

6.2 “Minimizing Wire Delays by Net-Topology Aware Binding During Floorplan-Driven High Level Synthesis,” Vyas Krishnan and Srinivas Katkoori (Univ. of South Florida)

5.3 “AC_Coupling Strategy for High-Speed Transceivers of 10 Gbps and Beyond,” Yikui (Jen) Dong, Steve Howard, Freeman Zhong, Scott Lowrie, Ken Paradis, Jan Kolnik, and Jeff Burleson (LSI Logic)

6.3 “SWORD: A SAT Like Prover Using Word Level Information,” Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, and Rolf Drechsler  (Univ. of Bremen, Germany

Tuesday, Oct. 16

8-8:30 a.m.

Registration/Breakfast

8:30-9:30 p.m.

Keynote: James Meindl
Chair: Vincent Mooney

9:30-10 a.m.

Break

10-11:30 a.m.

Session 7
New Devices
Chair: Sung Kyu Lim (Georgia Tech)

Session 8 (Special Session 1)
Reconfigurable and Hybrid System
Chair: Hsien-Hsin Sean Lee (Georgia Tech)

7.1 “A High-Driving Class-AB Buffer Amplifier with a New Pseudo Source Follower,” Chih-Wen Lu and Yen-Chih Shen (National Chi Nan Univ.)

8.1 “Computing and Design for Software and Silicon Manufacturing,” Davide Pandini, Giuseppe Desoli, and Alessandro Cremonesi (STMicroelectronics)

7.2 “A New Analytical Approach of the Impact of Jitter on Continuous Time Delta Sigma Converters,” Julien Goulier and Eric Andre (STMicroelectronics) and Marc Renaudin (TIMA)

8.2 “Adaptive Genetic Algorithm for Dynamically Reconfigurable Modules Allocation,” Vincenzo Rana, Chiara Sandionigi, Marco Domenico Santambrogio, and Donatella Sciuto (Politecnico di Milano)

7.3 “Transistor Level Automatic Layout Generator for Non-Complementary CMOS Cells,” Adriel Ziesemer, Cristiano Lazzari, and Ricardo Reis (UFRGS)

8.3 “New Tool Support and Architectures in Adaptive Reconfigurable Computing,” Jürgen Becker, Michael Hübner, and Adam Donlin (Universität Karlsruhe and Xilinx)

11:30-1 p.m.

Lunch

1-2:30 p.m.

Session 9
Special Purpose Design Optimization
Chair: Qinru Qiu (Binghamton Univ.)

Session 10 (Special Session 2)
Architecture Design Principles
Chair: Juergen Becker (Universitaet Karlsruhe) and Marco D. Santambrogio (Politecnico di Milano)

B9.1 Rate-Based Scheduling Police for QoS Flows in Networks on Chip,” Aline Mello, Ney Calazans, and Fernando Moraes (Pontificai Universidade Catolica Do Rio Grande do Sul

10.1 “Simulation of Hybrid Computer Architectures:  Simulators, Methodologies, and Recommendations,” Pranav Vaidya and Jaehwan Lee (Indiana Univ.-Purdue Univ., Indianapolis)

9.2 “Parallelized Radix-2 Scalable Montgomery Multiplier,” Nan Jiang and David Harris (Harvey Mudd College)

10.2 “New Parallel Programming Techniques for Hardware Design,” Satnam Singh (Microsoft Research)

9.3 “An Efficient Heterogeneous Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor,” Behnam Ghavami, Arash Medizadeh, Morteza SahebZamani, Hossein Pedram, and Farhad Mehdipour (Amirkabir Univ. of Technology)

10.3 “Efficient DSP Algorithm Development for FPGA and ASIC Technologies,” Jason Calderwood

2:30-3:30 p.m.

Break/Poster

3:30-5 p.m.

Panel: Chairs and Panelists
Panel Discussion Title: "System-In-Package vs. System-on-Chip"

The ever increasing demand for ultra high integration density for fully integrated systems poses very interesting challenges to system designers. Of late, several groups have claimed the advantages of System-In-Package (SIP) over System-on-Chip (SoC) in some particular applications. The comparison between the two approaches involves analysis in many different aspects: design, fabrication, packaging, test, CAD tools, and system reliability. The panel will discuss the advantages and disadvantages of SoC and SIP to help pioneer future research and developments.

Panel Members:
- Dr. Rao R Tummala, Professor; Joseph M. Pettit Chair in Electronics Packaging; Director, NSF Packaging Research Center; GRA Eminent Scholar, Georgia Institute of Technology
- Dr. Madhavan Swaminathan, Joseph M. Pettit Professor in Electronics; Professor; Deputy Director, Microsystems Packaging Research Center, Georgia Institute of Technology
- Dr. Salvador Mir, Reliable Mixed-signal Systems Group Leader, Techniques of Informatics and Microelectronics for Computer Architecture

Organizer: Dr. Byunghoo Jung, Assistant Professor, Purdue University

5-6 p.m.

Break (Buses leave at 5:30 p.m.)

6-10 p.m.

Conference Party, King Center

Wednesday, Oct. 17

8-8:30 a.m.

Registration/Breakfast

8:30-9:30 a.m.

Keynote: Gene A. Frantz
Chair: Paul Hasler

9;30-10 a.m.

Break

10-11;30 a.m.

Session 11
Physical Design and Test
Chair: Frank K. Gurkaynak (Ecole Polytechnique Federale de Lausanne)

Session 12
Signal and Image Processing
Chair: Wei-Chung Cheng (National Chiao-Tung Univ.)

11.1 “Incremental Placement for Structured ASICs Using the Transportation Problem,” Andrew Ling*, Deshanand Singh**, and Stephen Brown** (Univ. of Toronto; ** Altera Corp.)

12.1 ”A Low-Power Deblocking Filter Architecture for H.264 Advanced Video Coding,” Jaemoon Kim, Sangkwon Na, and Chong-Min Kyung
(KAIST)

11.2 “Test Data Compression and TAM Design,” Julien Dalmasso, Marie-Lise Flottes, and Bruno Rouzeyr (Univ. of Montpellier)

12.2 “The Hazard-Free Superscalar Pipeline Fast Fourier Transform Algorithm and Architecture,”Bassam Mohd (Qualcomm), Adnan Aziz, and Earl Swartzlander (Univ. of Texas)

11.3 “Dynamic Gates with Hysteresis and Configurable Noise Tolerance,” Kenneth Stevens and Krishna Santhanam

12.3 “An Efficient H.264 Intra Frame Coder System Design,” Ilker Hamzaoglu, Ozgur Tasdizen, and Esra Sahin (Sabanci Univ.)

11:30 a.m.-1 p.m.

Lunch

1-2:30 p.m.

Session 13
Verification and Validation
Chair:  Byunghoo Jung (Purdue Univ.)

Session 14
Estimation and Evaluation
Chair: Yunsi Fei (Univ. of Connecticut)

13.1 “Qualification of Behavioral Level Design Validation for AMS & RF SoC,” Yves Joannon (LCIS-ESISAR) and Vincent Beroulle, Chantal Robach, Smail Tedjini, and Jean-Louis Carbonero (STMicroelectronics)

14.1 “Fast Estimation of Software “Energy Consumption Using IPI (Inter-Prefecth Interval) Energy Model,” Jungsoo Kim, Kyungsu Kang, Heejun Shim, and Chong-Min Kyung (KAIST)

13.2 “Evaluating Memory Sharing Data Size and TCP Connections in the Performance of a Reconfigurable Hardware-based Architecture for TCP/IP Stack,” Jean Carlo Hamerski, Everton Reckziegel, and Fernanda Kastensmidt (UFRGS)

14.2 ““Power Optimization for Conditional Task Graphs in DVS Enabled Multiprocessor Systems,” Parth Malani, Prakash Mukre, and Qinru Qiu (Binghamton Univ.)

13.3 “Impact of Hardware Emulation on the Verification Quality Improvement,” Youssef Serrestou, Vincent Beroulle, and Chantal Robach (ICIS-INPG)

14.3 “ A Minimum-Latency Block-Serial Architecture of a Decoder for IEEE 802.11n LDPC Codes,” Massimo Rovini, Giuseppe Gentile, Francesco Rossi, and Luca Fanucci (Univ. of Pisa) 

2:30 – 3:30 p.m.

Break/Ph.D. Forum

3:30 –5:00 p.m.

Session 15
New Devices for Mixed Signal
Chair: Salvador Mir (TIMA)

Session 16
Low Power Design
Chair: Jaehwan (John) Lee, Indiana University-Purdue University Indianapolis

15.1 Full Custom Design of a Three-Stage Amplifier with 5500MHz·pF/mW Performance in 0.18um CMOS,” Run Chen, Liyuan Liu, Dongmei Li, and Zhihua Wang (Tsinghua Univ.)

16.1 “A Bit-sliced, Scalable and Unified Montgomery Multiplier Architecture for RSA and ECC,” Sudhakar M, Kamala R.V and Srinivas M.B (IIIT- Hyderabad)

15.2 “A 128dB Dynamic Range 1kHz Bandwidth Wereo ADC with 114dB THD,” Yuqing Yang, Sculley Terry (Texas Instruments), and Jacob Abraham (University of Texas-Austin)

16.2 “Low Power On-Chip Thermal Sensors Based on Wires,” Basab Datta and Wayne Burleson (University of Massachusetts)

16.3 “Low-Power CAM with 12-Transistor Design Cell”, Saleh Abdel-Hafeez, (Jordan University of Science and Technology) and Shadi M Harb and William R Eisenstadt (University of Florida)